logo_sispad
SISPAD 2004

September 2-4, 2004, Munich, Germany

ieee

eds

Conference Program




Saturday, September 4, 2004


Author Index >>


Session 16:  Advanced Compact Models

Location: Conference Room London


14:00 Optimization of Recessed and Elevated Silicide Source/Drain Contact Structure Using Physical Compact Resistance Modeling and Simulation in Ultra-Thin Body SOI MOSFETs
Kim1, S.-D., Johnson1, J. B., Yuan2, J., Woo2, J. C. S.

1 IBM Systems & Technology Group, Essex Junction, USA
2 Electrical Eng. Dept., University of California, Los Angeles, USA


14:20
A New Backscattering Model for Nano-MOSFET Compact Modeling
Fuchs1,2, E., Dollfus2 P., Lecarval3, G., Robilliart1, E., Barraud3, S., Villanueva4, D., Jaouen1, H.

1 STMicroelectronics, Crolles, France
2 IEF, CNRS-UPS Orsay, France
3 CEA-SRD-DTS-LSPC, Grenoble, France
4 Philips Semiconductors, Crolles, France


14:40
Fully-Depleted SOI-MOSFET Model for Circuit Simulation and its Application to 1/f Noise Analysis
Sadachika1, N., Uetsuji1, Y., Kitamaru1, D.,Mattausch1, H. J., Miura-Mattausch1, M., Weiss2, L., Feldmann2, U., Baba3, S., 

1 Graduate School of Advanced Sciences of Matter, Hiroshima University, Japan
2 Infineon Technologies, Munich, Germany
3 Oki Electric Industry, Tokyo, Japan


15:00 Coffee Break


15:30
Modeling of Carrier Transport Dynamics at GHz-Frequencies for RF Circuit-Simulation
Navarro1, D., Nakayama2, N., Machida3, K., Takeda1, S. Chiba1, Y., Ueno1, H., Mattausch1, H. J., Miura-Mattausch1, M., Ohguro2, T., Iizuka2, T., Taguchi2, M., Miyamoto2, S.

1 Graduate School of Advanced Sciences of Matter, Hiroshima University, Japan
2 Semiconductor Technology Academic Research Center, Yokohama, Japan
3 Mathematical Systems, Inc., Tokyo, Japan


15:50
SPICE-Compatible Macro Model for Split-Gate Compact NVM Cell with Various Gap Sizes
Akil1, N., van Langevelde2, R., Goarin1, P., van Duuren1, M., Slotboom1, M.

1 Philips Research Leuven, Leuven, Belgium
2 Philips Research, Eindhoven, The Netherlands


16:10
SET Accurate Compact Model for SET-MOSFET Hybrid Circuit Simulation
Le Royer1, C., Le Carval1, G., Sanquer2, M.

1 CEA-DRT-LETI - CEA/GRE, 17 Grenoble, France
2 CEA-DRFMC, Grenoble, France