Session 13: Strained MOSFET
Analysis
Location: Conference
Room New York
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| 11:00 |
Very
High Performance, Sub-20nm, Strained Si and Six Ge1-x,
Hetero-structure, Center Channel (CC) NMOS and PMOS DGFETs
Krishnamohan1,
T., Jungemann2, C., Saraswat1, K. C.
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|
1
Department of Electrical Engineering, Stanford University, Stanford
2 Technical University of Braunschweig,
Braunschweig, Germany |
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|
11:20
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Scalability
of FinFETs and Unstrained-Si/Strained-Si FDSOI-MOSFETs
Bufler,
F. M., Schenk, A., Fichtner, W.
|
|
Institut
für Integrierte Systeme, ETH Zürich, Switzerland |
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11:40
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Device
performance in conventional and strained Si n-MOSFETs with high-k gate
stacks
Yang,
L., Watling, J. R., Asenov, A., Barker, J. R., Roy, S.
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Device
Modelling Group, Department of Electronics and Electrical Engineering,
University of Glasgow, UK |
|
|
| 12:00
|
Understanding
the role of strain in Si-Ge devices
Choudhary1,
D., Catherwood1, J., Clancy1, P., Murthy2,
C.S.
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1
School of Chemical Engineeering, Cornell University, Ithaca, USA
2 IBM-East Fishkill, USA |
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