2003 International Conference on Simulation of Semiconductor Processes and Devices

September 3-5, 2003 • Boston Marriott Cambridge • Cambridge • MA • USA

Companion workshop to be held at MIT
Saturday, Sept. 6, 2003, (8:30am to 5pm)
MIT Tang Center, Building E51

"Modeling and Simulation Issues in Strained Si MOSFETs"

Organizers: Judy Hoyt; Dimitri Antoniadis, MIT

The workshop will begin with introductory overviews highlighting the basics of strained Si/relaxed SiGe materials and device technology. These reviews will be followed by a series of talks on strained silicon modeling and simulation issues including: modeling of carrier transport in strained Si, the impact of strain and energy bands on performance scaling (Ion/Ioff) of strained Si MOSFETs, theory of strain relaxation and defects in strained Si and relaxed SiGe, process modeling (e.g. dopant and Ge diffusion), stress modeling in complex device structures, and device self-heating.

Registration information: The registration fee is $100 (includes continental breakfast, coffee breaks, and lunch). To register fill out the registration form and send to Fely Barrera, CISX 332, Stanford University, Stanford, CA 94305-4075. Checks should be made payable to IEEE/SISPAD03.

Hotel: A block of rooms has been reserved at the Boston Marriott Cambridge.

Website for map of workshop location: http://whereis.mit.edu/

last update: July 10, 2003