Technical Program:
September 3, 2003
September 4, 2003,
Poster Session
Session 6 - Front End Process Physics
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8:30 - 9:15 I-7 |
"Dopant Diffusion Under Pressure and Stress" M. Aziz, Harvard University, Cambridge, MA |
| 9:15 - 9:40 6-1 |
"Investigation of the Detailed Structure of Atomically Sharp Ge/SiO2 Interfaces" T. Liang, W. Windl, S. Lopatin*, G. Duscher,* The Ohio State University, Columbus, OH and *North Carolina State University, Raleigh, NC |
| 9:40 - 10:05 6-2 |
"Ab-initio Calculations to Predict Stress Effects on Defects and Diffusion in Silicon" M. Diebel, S. T. Dunham, University of Washington, Seattle, WA |
| Break (15 minutes) | |
| 10:20 - 10:45 6-3 |
"Atomistic Modeling of B Activation and Deactivation for Ultra-shallow Junction Formation" M. Aboy, L. Pelaz, A. Mokhberi*, Y. Takamura*, P. B. Griffin*, J. D. Plummer*, L. A. Marques, J. Barbolla, University of Valladolid, Valladolid, Spain and *Stanford University, Stanford, CA |
| 10:45 - 11:10 6-5 |
"Simulation of Surface Engineering for Ultra Shallow Junction Formation of PMOS for the 90nm CMOS Technology Node and Beyond" J. Bonnouvrier, D. Lenoble, E. Robilliart, T. Schwartzann, H. Jaouen, STMicroeletronics, Crolles, France |
| 11:10 - 11:35 6-6 |
"Modeling the Effect of Source/Drain Sidewall Spacer Process on Boron Ultra Shallow Junctions" S. Chakravarthi, P. Kohli*, P. R. Chidambaram, H. Bu, A. Jain, B. Hornung, C. F. Machala, Texas Instruments Inc., Dallas, TX and *University of Texas, Austin, TX |
Session 7 - Quantum Effects and TCAD Applications | |
8:50 - 9:15 7-1 |
"Electrostatic Analysis of Carbon Nanotube Arrays" X. Wang, H.-S. P. Wong, P. Oldiges, R. J. Miller, IBM Semiconductor Research and Development Center, Hopewell Junction, NY |
| 9:15 - 9:40 7-2 |
"Theory and Design of Field-Effect Carbon Nanotube Transistors" G. Pennington, N. Goldsman, University of Maryland, College Park, MD |
| 9:40 - 10:05 7-3 |
"Comparison of Numerical Quantum Device Models" H. Kosina, G. Klimeck*, M. Nedjalkov, S. Selberherr, TU Vienna, Vienna, Austria and *California Institute of Technology, Pasadena, CA |
| Break (15 minutes) | |
| 10:20 - 10:45 7-4 |
"Energy Dissipation in Mesoscopic Circuits" B. Soree, W. Magnus, W. Schoenmaker, IMEC, Leuven, Belgium |
| 10:45 - 11:10 7-5 |
"A FinFET Design Based on Three-Dimensional Process and Device Simulations" M. Kondo, R. Katsumata, H. Aochi, T. Hamamoto, S. Ito, N. Aoki, T. Wada, Toshiba Corporation, Yokohama, Japan |
| 11:10 - 11:35 7-6 |
"Accurate Transport Modeling with 2D Dopant Profile Effect in Leff ~ 20nm MOSFETs via Inverse Modeling" T. Tanaka, H. Kanata, Y. Tagawa, S. Satoh, T. Sugii, Fujitsu Limited, Tokyo, Japan |
| 11:35 - 12:00 7-7 |
"Optimization of Sub-50nm MOSFETs to Mitigate Drive Current Degradation Due to Silicon Recess in S/D" Y. Shiho, B. Winstead, M. Foisy, M. Orlowski, Motorola Digital DNA Laboratories, Austin, TX |
Session 8 - Heterojunction Device Physics | |
| 1:30 - 1:55 8-1 |
"Maximum Drive Current Scaling Properties of Strained Si NMOS in the Deca-Nanometer Regime" C. Jungemann, B. Meinerzhagen*, Stanford University, Stanford, CA and *University of Bremen, Bremen, Germany |
| 1:55 -2:20 8-2 |
"Computer Aided Design of Sub-100nm Strained-Si/Si 1-x Gex NMOSFET through Integrated Process and Device Simulations" A. V.-Y. Thean, A. L. Barr, T. R. White, Z.-H. Shi, B.-Y. Nguyen, C.-L. Liu, K. Beardmore, J. Z.-X. Jiang, P. Lerma, E. Duda, M. Sadaka, M. Orlowski, B. E. White, Jr., J. Mogab, Motorola, Austin, TX |
| 2:20 - 2:45 8-3 |
"Device Design of SiGe HBTs with Low Distortion Characteristics using Harmonic Balance Device Simulator" J. Sato-Iwanaga, A. Asai, T. Takagi, M. Tanabe, Z. Yu*, R. W. Dutton*, Matsushita Electric Industrial Co., Ltd., Moriguchi, Osaka, Japan and *Stanford University, Stanford, CA |
| Break (15 minutes) | |
| 3:00 - 3:25 8-4 |
"Implications of Gate Design on RF Performance of Sub-100nm Strained-Si/SiGe nMODFETs" Q. Ouyang , S. J. Koester, J. O. Chu, K. L. Saenger, J. A. Ott, K. A. Jenkins, IBM T.J. Watson Research Center, Yorktown Heights, NY |
| 3:25 - 3:50 8-5 |
"Grain Boundary Effects on Subthreshold Behaviour in Single Grain Boundary nano-TFTs" P. M. Walker, H. Mizuta, Y. Furuta*, Cavendish Laboratory, Cambridge, United Kingdom and *Osaka University, Osaka, Japan |
| 3:50 - 4:15 8-7 |
"A Study on Cell Characteristics of PRAM using the Phase-Change Simulation" Y.-T. Kim, K.-H. Lee, W.-Y. Chung, T.-K. Kim, Y.-K. Park, J.-T. Kong, Samsung Electronics Co. Ltd, Kyunggi-Do, Korea |
Session 9 - Compact Models | |
| 1:30 - 1:55 9-1 |
"Compact Modeling of Flash Memory Cells Including Substrate-Bias-Dependent Hot-Electron Gate Current" K. Sonoda, M. Tanizawa, S. Shimizu, Y. Araki, S. Kawai, T. Ogura, S. Kobayashi, K. Ishikawa, Y. Inoue, N. Kotani**, Mitsubishi Electric Corp., Hyogo, Japan and *Hiroshima International University, Hiroshima, Japan |
| 1:55 - 2:20 9-2 |
"Simulation of the Circuit Performance Impact of Lithography in Nanoscale Semiconductor Manufacturing" M. Choi, L. Milor, L. Capodieci*, Georgia Institute of Technology, Atlanta, GA and *Advanced Micro Devices, Sunnyvale, CA |
| 2:20 - 2:45 9-3 |
"Physical Compact Model for Threshold Voltage in Short-Channel Double-Gate Devices" K. Kim, J. G. Fossum*, C.-T. Chuang, IBM T.J. Watson Research Center, Yorktown Heights, NY and *University of Florida, Gainesville, FL |
| Break (15 minutes) | |
| 3:00 - 3:25 9-4 |
"Quantum Surface Potential Model Suitable for Advanced MOSFETs Simulation" F. Pregaldiny, C. Lallement, D. Mathiot, ERM-PHASE, Illkirch, France |
| 3:25 - 3:50 9-5 |
"An Efficient Method for Frequency-domain Simulation of Short Channel MOSFET Including the Non-Quasistatic Effect" K.-I. Lee, C. Lee*, H. Shin**, Y.-J. Park, H. S. Min, Seoul National University, Seoul, Korea, *Soongsil University, Seoul, Korea and **Ewha Womans University, Seoul, Korea |
| 3:50 - 4:15 9-6 |
"Simulation of Electronic Control in Electroosmotic Flow Channels" T. Dudar, O. Mikulchenko*, N. Aluru**, K. Mayaram, Oregon State University, Corvallis, OR, *Intel Corporation, Sacramento, CA and **University of Illinois at Urbana-Champaign, Urbana, IL |
| 4:15 - 4:40 9-7 |
"A New Comprehensive SRAM Soft Error Simulation Based on 3D Device Simulation Incorporating Neutron Nuclear Reactions" M. Hane, Y. Kawakami, H. Nakamura*, T. Yamada*, K. Kumagai*, Y. Watanabe**, NEC Corporation, Sagamihara, Japan, *NEC Electronics Corporation, Japan and **Kyushu University, Japan |